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2,473
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Cryptographic Hardware and Embedded Systems – CHES 2005
Improved Higher-Order Side-Channel Attacks with FPGA Experiments
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Author(s):
Eric Peeters
,
François-Xavier Standaert
,
Nicolas Donckers
,
Jean-Jacques Quisquater
Publication date
(Print):
2005
Publisher:
Springer Berlin Heidelberg
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Finite Mixture Models
Geoffrey McLachlan
,
David Peel
(2000)
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Correlation Power Analysis with a Leakage Model
Eric Brier
,
Christophe Clavier
,
Francis Olivier
(2004)
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An Implementation of DES and AES, Secure against Some Attacks
Mehdi-Laurent Akkar
,
Christophe Giraud
(2001)
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Book Chapter
Publication date (Print):
2005
Pages
: 309-323
DOI:
10.1007/11545262_23
SO-VID:
db3b3e43-9fd2-4efe-89c8-fc907c6d6f78
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Book chapters
pp. 383
The “Backend Duplication” Method
pp. 30
A Stochastic Model for Differential Side Channel Cryptanalysis
pp. 412
Efficient Hardware for the Tate Pairing Calculation in Characteristic Three
pp. 75
Energy-Efficient Software Implementation of Long Integer Modular Arithmetic
pp. 157
Successfully Attacking Masked AES Hardware Implementations
pp. 172
Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints
pp. 187
Masking at Gate Level in the Presence of Glitches
pp. 293
On Second-Order Differential Power Analysis
pp. 309
Improved Higher-Order Side-Channel Attacks with FPGA Experiments
pp. 339
Data Remanence in Flash Memory Devices
pp. 427
AES on FPGA from the Fastest to the Smallest
pp. 441
A Very Compact S-Box for AES
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