Advanced CMOS Gate Stack: Present Research Progress

Abstract

The decreasing sizes in complementary metal oxide semiconductor (CMOS) transistor technology require the replacement of SiO ₂ with gate dielectrics that have a high dielectric constant (high- k). When the SiO ₂ gate thickness is reduced below 1.4 nm, electron tunneling effects and high leakage currents occur which present serious obstacles for device reliability. In recent years, various alternative gate dielectrics have been researched. Following the introduction of HfO ₂ into the 45 nm process by Intel in 2007, the screening and selection of high- k gate stacks, understanding their properties, and their integration into CMOS technology have been a very active research area. This paper reviews the progress and efforts made in the recent years for high- k dielectrics, which can be potentially integrated into 22 nm (and beyond) technology nodes. Our work includes deposition techniques, physical characterization methods at the atomic scale, and device reliability as the focus. For most of the materials discussed here, structural and physical properties, dielectric relaxation issues, and projections towards future applications are also discussed.