A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS

Chen, Gregory; Anders, Mark A.; Kaul, Himanshu; Satpathy, Sudhir K.; Mathew, Sanu K.; Hsu, Steven K.; Agarwal, Amit; Krishnamurthy, Ram K.; De, Vivek; Borkar, Shekhar

doi:10.1109/JSSC.2014.2369508

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A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS

Author(s): Gregory Chen , Mark A. Anders , Himanshu Kaul , Sudhir K. Satpathy , Sanu K. Mathew , Steven K. Hsu , Amit Agarwal , Ram K. Krishnamurthy , Vivek De , Shekhar Borkar

Publication date (Print): January 2015

Journal: IEEE Journal of Solid-State Circuits

Publisher: Institute of Electrical and Electronics Engineers (IEEE)

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Æthereal Network on Chip:Concepts, Architectures, and Implementations

J. Dielissen, K Goossens, A Radulescu (2005)

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A 167-Processor Computational Platform in 65 nm CMOS

Anh Tran, Zhibin Xiao, Dean Truong … (2009)

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ORION 2.0: A Power-Area Simulator for Interconnection Networks

Andrew B. Kahng, Bin Li, Li-Shiuan Peh … (2012)

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Title: IEEE Journal of Solid-State Circuits

Abbreviated Title: IEEE J. Solid-State Circuits

Publisher: Institute of Electrical and Electronics Engineers (IEEE)

ISSN (Print): 0018-9200

ISSN (Electronic): 1558-173X

Publication date Created: January 2015

Publication date (Print): January 2015

Volume: 50

Issue: 1

Pages: 59-67

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DOI: 10.1109/JSSC.2014.2369508

SO-VID: 002cb0a1-6253-436d-85d5-b165cc1ad796

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A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS

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2023 Research and Innovation Open Distance and eLearning (ODeL) Hybrid Conference

Most cited references 8

Æthereal Network on Chip:Concepts, Architectures, and Implementations

A 167-Processor Computational Platform in 65 nm CMOS

ORION 2.0: A Power-Area Simulator for Interconnection Networks

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