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      MIS: A Multiple-Level Logic Optimization System

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          Logic Minimization Algorithms for VLSI Synthesis

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            A VLSI RISC

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              Logic Synthesis Through Local Transformations

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                Author and article information

                Journal
                IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
                IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.
                Institute of Electrical and Electronics Engineers (IEEE)
                0278-0070
                November 1987
                November 1987
                : 6
                : 6
                : 1062-1081
                Article
                10.1109/TCAD.1987.1270347
                cd613d0a-eecf-4d58-8829-9abfa9c9ee2f
                © 1987
                History

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