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Cryptographic Hardware and Embedded Systems – CHES 2005
A Very Compact S-Box for AES
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Author(s):
D. Canright
Publication date
(Print):
2005
Publisher:
Springer Berlin Heidelberg
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A Compact Rijndael Hardware Architecture with S-Box Optimization
Akashi Satoh
,
Sumio Morioka
,
Kohji Takano
…
(2001)
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Efficient Rijndael Encryption Implementation with Composite Field Arithmetic
Atri Rudra
,
Pradeep K. Dubey
,
Charanjit Jutla
…
(2001)
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An ASIC Implementation of the AES SBoxes
Johannes Wolkerstorfer
,
Elisabeth Oswald
,
Mario Lamberger
(2002)
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Book Chapter
Publication date (Print):
2005
Pages
: 441-455
DOI:
10.1007/11545262_32
SO-VID:
ad242389-15ed-45b6-9c2f-892cf16b788e
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Book chapters
pp. 383
The “Backend Duplication” Method
pp. 30
A Stochastic Model for Differential Side Channel Cryptanalysis
pp. 412
Efficient Hardware for the Tate Pairing Calculation in Characteristic Three
pp. 75
Energy-Efficient Software Implementation of Long Integer Modular Arithmetic
pp. 157
Successfully Attacking Masked AES Hardware Implementations
pp. 172
Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints
pp. 187
Masking at Gate Level in the Presence of Glitches
pp. 293
On Second-Order Differential Power Analysis
pp. 309
Improved Higher-Order Side-Channel Attacks with FPGA Experiments
pp. 339
Data Remanence in Flash Memory Devices
pp. 427
AES on FPGA from the Fastest to the Smallest
pp. 441
A Very Compact S-Box for AES
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