Simultaneous switching noise in on-chip CMOS power distribution networks

Tang, K.T.; Friedman, E.G.

doi:10.1109/TVLSI.2002.800533

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Simultaneous switching noise in on-chip CMOS power distribution networks

Author(s): K.T. Tang , E.G. Friedman

Publication date (Print): August 2002

Journal: IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Publisher: Institute of Electrical and Electronics Engineers (IEEE)

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Most cited references 16

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Modeling and simulation of insulated-gate field-effect transistor switching circuits

H. Shichman, D.A. Hodges (1968)

0 comments Cited 65 times – based on 0 reviews      Review now

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A 200-MHz 64-b dual-issue CMOS microprocessor

R. Allmon, R.T. Witek, D.W. Dobberpuhl … (1992)

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CMOS Circuit Speed and Buffer Optimization

N. Hedenstierna, K.O. Jeppson (1987)

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Author and article information

Journal

Title: IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Abbreviated Title: IEEE Trans. VLSI Syst.

Publisher: Institute of Electrical and Electronics Engineers (IEEE)

ISSN (Print): 1063-8210

ISSN (Electronic): 1557-9999

Publication date Created: August 2002

Publication date (Print): August 2002

Volume: 10

Issue: 4

Pages: 487-493

Article

DOI: 10.1109/TVLSI.2002.800533

SO-VID: 8618624c-aa84-469e-ae49-783195d65ff4

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