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Cryptographic Hardware and Embedded Systems - CHES 2007
MAME: A Compression Function with Reduced Hardware Requirements
other
Author(s):
Hirotaka Yoshida
,
Dai Watanabe
,
Katsuyuki Okeya
,
Jun Kitahara
,
Hongjun Wu
,
Özgül Küçük
,
Bart Preneel
Publication date
(Print):
2007
Publisher:
Springer Berlin Heidelberg
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SDG 10: Reduced Inequalities
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The MD5 Message-Digest Algorithm
R. Rivest
(1992)
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Differential Power Analysis
Paul Köcher
,
Joshua Jaffe
,
Benjamin Jun
(1999)
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Linear Cryptanalysis Method for DES Cipher
Mitsuru Matsui
(1994)
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Book Chapter
Pages
: 148-165
DOI:
10.1007/978-3-540-74735-2_11
SO-VID:
7efd8210-c3d6-4b32-b7a3-80fb3bce9c72
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Book chapters
pp. 181
Secret External Encodings Do Not Prevent Transient Fault Analysis
pp. 272
How to Maximize the Potential of FPGA Resources for Modular Exponentiation
pp. 28
Side Channel Cryptanalysis of a Higher Order Masking Scheme
pp. 45
High-Speed True Random Number Generation with Logic Gates Only
pp. 63
FPGA Intrinsic PUFs and Their Use for IP Protection
pp. 81
Evaluation of the Masked Logic Style MDPL on a Prototype Chip
pp. 121
On the Power of Bitslice Implementation on Intel Core2 Processor
pp. 148
MAME: A Compression Function with Reduced Hardware Requirements
pp. 209
AES Encryption Implementation and Analysis on Commodity Graphics Processing Units
pp. 427
Information Theoretic Evaluation of Side-Channel Resistant Logic Styles
pp. 450
PRESENT: An Ultra-Lightweight Block Cipher
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