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      HADES: Microprocessor Hazard Analysis via Formal Verification of Parameterized Systems

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          Abstract

          HADES is a fully automated verification tool for pipeline-based microprocessors that aims at flaws caused by improperly handled data hazards. It focuses on single-pipeline microprocessors designed at the register transfer level (RTL) and deals with read-after-write, write-after-write, and write-after-read hazards. HADES combines several techniques, including data-flow analysis, error pattern matching, SMT solving, and abstract regular model checking. It has been successfully tested on several microprocessors for embedded applications.

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          Tools and Algorithms for the Construction and Analysis of Systems

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            Parameterized verification through view abstraction

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              Solver technology for system-level to RTL equivalence checking

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                Author and article information

                Journal
                2016-12-15
                Article
                10.4204/EPTCS.233.9
                1612.04986
                60048799-df11-44bd-978b-7a5e37ce1b63

                http://arxiv.org/licenses/nonexclusive-distrib/1.0/

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                Custom metadata
                EPTCS 233, 2016, pp. 87-93
                In Proceedings MEMICS 2016, arXiv:1612.04037
                cs.AR
                EPTCS

                Hardware architecture
                Hardware architecture

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