Case study in RSFQ design: fast pipelined parallel adder

Litskevitch, P.; Bunyk, P

doi:10.1109/77.783835

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Case study in RSFQ design: fast pipelined parallel adder

Author(s): P. Bunyk , P. Litskevitch

Publication date (Print): June 1999

Journal: IEEE Transactions on Appiled Superconductivity

Publisher: Institute of Electrical and Electronics Engineers (IEEE)

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Most cited references 12

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RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systems

K.K. Likharev, V.K. Semenov (1991)

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A Regular Layout for Parallel Adders

Kung, Brent (1982)

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A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations

Harold S. Stone, Peter M. Kogge (1973)

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Author and article information

Journal

Title: IEEE Transactions on Appiled Superconductivity

Abbreviated Title: IEEE Trans. Appl. Supercond.

Publisher: Institute of Electrical and Electronics Engineers (IEEE)

ISSN (Print): 10518223

Publication date (Print): June 1999

Volume: 9

Issue: 2

Pages: 3714-3720

Article

DOI: 10.1109/77.783835

SO-VID: 132f2d88-d2c9-4edd-af7d-28622a800b93

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