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      Computer Aided Verification 

      An automata-theoretic approach to fair realizability and synthesis

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      Springer Berlin Heidelberg

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          The temporal logic of programs

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            On the synthesis of a reactive module

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                Book Chapter
                1995
                May 31 2005
                : 267-278
                10.1007/3-540-60045-0_56
                7f4f636e-e384-42bb-8a17-f82383f2c9a7
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