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Cryptographic Hardware and Embedded Systems - CHES 2002
Experience Using a Low-Cost FPGA Design to Crack DES Keys
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Author(s):
Richard Clayton
,
Mike Bond
Publication date
(Online):
February 17 2003
Publisher:
Springer Berlin Heidelberg
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Special Feature Exhaustive Cryptanalysis of the NBS Data Encryption Standard
W. Diffie
,
M.E. Hellman
(1977)
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On the Security of DES
Adi Shamir
(1986)
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Efficient hardware and software implementations for the DES
Marc Davio
,
Yvo Desmedt
,
Jo Goubert
…
(2024)
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Book Chapter
Publication date (Print):
2003
Publication date (Online):
February 17 2003
Pages
: 579-592
DOI:
10.1007/3-540-36400-5_42
SO-VID:
5b62c44b-ec2a-4117-b163-b824e7f4df66
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Book chapters
pp. 2
Optical Fault Induction Attacks
pp. 144
2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis
pp. 13
Template Attacks
pp. 29
The EM Side—Channel(s)
pp. 579
Experience Using a Low-Cost FPGA Design to Crack DES Keys
pp. 172
An Optimized S-Box Circuit Architecture for Low Power AES Design
pp. 187
Simplified Adaptive Multiplicative Masking for AES
pp. 198
Multiplicative Masking and Power Analysis of AES
pp. 260
Fault Attacks on RSA with CRT: Concrete Results and Practical Countermeasures
pp. 291
The Montgomery Powering Ladder
pp. 415
True Random Number Generator Embedded in Reconfigurable Hardware
pp. 431
Evaluation Criteria for True (Physical) Random Number Generators Used in Cryptographic Applications
pp. 450
A Hardware Random Number Generator
pp. 454
RFID Systems and Security and Privacy Implications
pp. 593
A Time-Memory Tradeo. Using Distinguished Points: New Analysis & FPGA Results
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